The present invention relates generally to the field of electronic circuits and more particularly to circuits used for string comparison operations.
In high performance computing, being able to validate the correctness of a result is an important function. Frequently, these error detection methods need to be implemented within certain specific timing constraints, which introduces a need for a method that is both accurate and efficient. In some cases, these timing constraints are for the execution of the string comparison in addition to the error detection process. In those cases, having hardware that is capable of executing the string comparisons while simultaneously performing error detection makes it much easier to meet any required timing constraints.